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# ENTER =>
71 To Run User DMA
tests
# ENTER =>
# ENTER =>
98 To Quick Test (All Slots)
99 To Run Exhaustive Tests (All Tests/All Slots)
# ENTER =>
# ENTER =>
S
Q
To Run test 00-99 on slot S ie 112
TO EXIT Testbench
Customizing the Verification Testbench
The number of core instances in the verification testbench and the configuration of each core can be modified by editing
the coreconfig.vhd file. It is recommended that customers using the OEM version of Model Sim supplied with Libero
IDE modify the NSLOTS constant at the top of the coreconfig.vhd file to reduce the number of active cores to three.
This will decrease simulation time, but test coverage is reduced to 32-bit cores only.
The usertests.vhd file contains two example routines that perform Target transactions and Master transfers. These
routines can be used as starting points for adding additional tests if required. However, due to the complexity of the
verification testbench, Actel recommends that it not be modified, and that the simple user testbenches described in the
following sections be used as starting points for any user simulations. The verification testbench is provided to
demonstrate the core’s operation under multiple conditions.
120
v4.0
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